1. Field of the Invention
This invention relates to semiconductor fabrication processes, and more particularly, to a method for forming a plurality of gate oxide layers with various predefined thicknesses in mixed-mode or embedded circuitry formed in semiconductor wafers.
2. Description of Related Art
In integrated circuits with MOSFET (metal-oxide semiconductor field-effect transistor) devices, it is usually desired to form associated gate oxide layers with various predefined thicknesses so as to allow the MOSFET devices to have different operating voltages. For instance, at the 0.25 .mu.m (micrometer) submicron fabrication level, the thickness of the gate oxide layer in one MOSFET device with an operating voltage of 3.3 V (volt) is about 20.ANG. (angstrom) larger than that of the gate oxide layer in another MOSFET device with an operating voltage of 2.5 V. In IC layout schemes, it is a widely used practice to incorporate the 3.3 V I/O (input/output) devices together with the 2.5 V core circuitry in the same module. Therefore, in such an IC, the gate oxide layers are formed with different predefined thicknesses for either 3.3 V or 2.5 V operation. This kind of circuit is customarily referred to as a mixed-mode or embedded circuit. The mixed-mode circuit is widely used in semiconductor memory devices, such as dynamic random access memory (DRAM), I/O drivers, or various other high-voltage components.
A conventional method for forming gate oxide layers with various predefined thicknesses in a mixed-mode circuit is depicted in detail in the following with reference to FIGS. 1A through 1F. In the case of FIGS. 1A through 1F, for example, the method is directed to the forming of a first gate oxide layer with a first predefined thickness of 50 .ANG. and a second gate oxide layer with a second predefined thickness of 70 .ANG..
Referring first to FIG. 1A, in the first step, a semiconductor substrate 10, such as a silicon substrate, is prepared. Next, a pad oxide layer 12 is formed over the substrate 10, and then a silicon nitride layer 14 is formed over the pad oxide layer 12.
Referring next to FIG. 1B, a plurality of field oxide layers 11 (or trench isolations) are formed by local oxidation of silicon (LOCOS) or shallow-trench isolation (STI) over the substrate 10. These field oxide layers 11 divide the surface area of the wafer into at least one first active region 13 and one second active region 15. In the first active region 13, for example, an internal circuit is to be formed; while in the second active region 15, a peripheral circuit is to be formed. After this, the remaining portions of the silicon nitride layer 14 and the pad oxide layer 12 are entirely removed.
Referring further to FIG. 1C, in the subsequent step, a sacrificial oxide layer (not shown) is formed over the wafer to serve as a mask, and then an ion-implantation process is performed on the wafer so as to form N-wells or P-wells (not shown) in the substrate 10. In these wells, a first NMOS transistor for the internal circuit is to be formed in the first active region 13, while a second NMOS transistor for the peripheral circuit is to be formed in the second active region 15 in later steps. After this, the sacrificial oxide layer is removed. Then, an initial oxide layer 16, such as a layer of silicon dioxide, is formed over the entire top surface of the wafer.
Referring next to FIG. 1D, the subsequent step is to perform a photolithographic and etching process on the wafer so as to remove a selected portion of the initial oxide layer 16 that is layered directly on the first active region 13. The first active region 13 is therefore exposed, while the second active region 15 still remains covered by the initial oxide layer 16. Then, a cleaning process, such as plasma/wet etching, is performed to remove the photoresist layer 15.
Referring further to FIG. 1E, in the subsequent step, a first oxide layer 18, such as a layer of silicon dioxide, is formed over the entire top surface of the wafer to a predefined thickness of 50 .ANG. (this thickness is equal to the smaller of the two predefined thicknesses of the gate oxide layers). The thickness of the composite oxide layer 17 that is to be formed in the region 15 includes the thickness of the thicker oxide layer due to the existence of the initial oxide layer. Then, a conductive layer 19, such as a layer of polycide (a composition of polysilicon and silicide), is formed over the first gate oxide layer 18.
One portion of the first oxide layer 18 that is layered in the first active region 13 serves as the desired first gate oxide layer with a thickness of 50 .ANG.; while the portion of the first gate oxide layer 18 that is layered in the second active region 15 and the underlying portion of the initial oxide layer 16 in combination form a composite oxide layer (designated collectively by the reference numeral 17 in FIG. 1E) which serves as the desired second gate oxide layer with a total thickness of 70 .ANG..
Referring finally to FIG. 1F, a photolithographic and etching process is then performed on the wafer so as to remove unwanted portions of the conductive layer 19, the oxide layer 18, and the initial oxide layer 16 until the top surface of the substrate 10 is exposed. One remaining portion of the conductive layer 19, as designated by the reference numeral 19a, serves as one gate electrode for the transistor that is to be formed in the first active region 13; while the other remaining portion of the same, as designated by the reference numeral 19b, serves as another gate electrode for another transistor that is to be formed in the second active region 15. The underlying portion of the oxide layer 18 beneath the gate electrode 19a serves as the desired first gate oxide layer with the first predefined thickness of 50 .ANG.; while the underlying portion of the composite oxide layer 17 beneath the gate electrode 19b serves the desired second gate oxide layer with the second predefined thickness of 70 .ANG..
One drawback to the foregoing method, however, is that the forming of the composite oxide layer would be difficult to be controlled precisely to the desired thickness since the composite oxide layer includes two oxide layers that are formed separately in different steps. As a result of this, the errors in the thickness of the two separate oxide layers due to fluctuations in the fabrication process will compound. The composite oxide layer is also poor in quality. Moreover, since in the removal of selected part of the oxide layer involves the steps of coating and removing photoresist layers, the gate oxide layers will be subjected to plasma damage and contamination by the photoresist.